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RF3145QuadBand GSM/EDGE/G SM850/DCS/ PCS Power Amplifier Module
RF3145
QUAD-BAND GSM/EDGE/GSM850/DCS/PCS POWER AMPLIFIER MODULE
RoHS Compliant & Pb-Free Product Package Style: Module (10 mm x 10 mm)
Features
Integrated Power Control & Band Select Single 3.0V to 4.8V Supply Voltage +35.0dBm GSM Output Pwr at 3.5V +33dBm DCS/PCS Output Pwr at 3.5V +29dBm 8PSK Output Pwr 53% GSM and 50% DCS/PCS PAE
NC 12 DCS IN 1 BAND SELECT 2 TX ENABLE 3 VBATT 4 VMODE 5 VRAMP 6 GSM IN 7 8 NC 9 GSM OUT 10 NC 11 DCS OUT
Applications
3V Dual/Triple/Quad-Band Mode Handsets Portable Battery-Powered Equipment GSM850 and GSM900 Products Commercial and Consumer Systems EDGE and GPRS Class 12 Compatible DCS/PCS Products
Functional Block Diagram
Product Description
The RF3145 is a high power, high efficiency power amplifier module with integrated power control. This module is self-contained with 50 input and output terminals. The device is manufactured on an advance Gallium Arsenide Heterojunction Bipolar Transistor (HBT) process, and has been designed for use as the final dual-mode GMSK/8PSK RF amplifier in GSM, DCS and PCS hand-held cellular equipment and other applications in the 824MHz to 849MHz, 880MHz to 915MHz, and in the 1710MHz to 1910MHz bands. Internal band select provides control to select the GSM850/GSM900 or DCS/PCS band. The device is packaged on ultra-small LCC, minimizing the required board space.
Ordering Information
RF3145 Quad-Band GSM/EDGE/GSM850/DCS/PCS Power Amplifier Module Power Amplifier Module, 5 Piece Sample Pack Fully Assembled Evaluation Board
RF3145PCBA-41X
Optimum Technology Matching(R) Applied
GaAs HBT GaAs MESFET InGaP HBT SiGe BiCMOS Si BiCMOS SiGe HBT GaAs pHEMT Si CMOS Si BJT GaN HEMT
RF MICRO DEVICES(R), RFMD(R), Optimum Technology Matching(R), Enabling Wireless ConnectivityTM, PowerStar(R), POLARISTM TOTAL RADIOTM and UltimateBlueTM are trademarks of RFMD, LLC. BLUETOOTH is a trademark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. (c)2006, RF Micro Devices, Inc.
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Absolute Maximum Ratings Parameter
Supply Voltage Power Control Voltage (VRAMP) Band Select TX Enable RF - Input Power Max Duty Cycle Output Load VSWR Operating Case Temperature Storage Temperature
Rating
-0.3 to +6.0 -0.3 to +1.8 3.0 3.0 12.0 50 10:1 -30 to +90 -55 to +150
Unit
V V V V dBm % C C
Caution! ESD sensitive device.
Exceeding any one or a combination of the Absolute Maximum Rating conditions may cause permanent damage to the device. Extended application of Absolute Maximum Rating conditions to the device may reduce device reliability. Specified typical performance or functional operation of the device under Absolute Maximum Rating conditions is not implied. RoHS status based on EUDirective2002/95/EC (at time of this document revision). The information in this publication is believed to be accurate and reliable. However, no responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any infringement of patents, or other rights of third parties, resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of RFMD. RFMD reserves the right to change component circuitry, recommended application circuitry and specifications at any time without prior notice.
Parameter
GSM US 850MHz Band
Operating Frequency Range Maximum Output Power
Min.
Specification Typ.
Max.
Unit
Condition
Temp=+25 C, VCC =3.5V, BandSel=Low, VMODE =Low, VRAMP =VRAMP,MAX, PIN =+4dBm Freq=824MHz to 849MHz, 25% Duty Cycle, Pulse Width=1154s, TX EN=High
824 +34.5 +35.4 +32.5
849
MHz dBm dBm Temp = 25C, VCC =3.5V, VRAMP =VRAMP,MAX Temp=+85oC, VBATT =3.0V, VRAMP =VRAMP,MAX VRAMP =0.2V At POUT,MAX, VCC =3.5V At POUT =31.5dBm F0 =849MHz, other signal 829MHz at 40dBm, measured at 869MHz in 100kHz RBW (Max Power) RBW=100kHz, 869MHz to 894MHz, POUT >+5dBm TX_ENABLE=0V, VRAMP =0.2, PIN =+6dBm Over all power levels Over all power levels Measured at DCS/PCS port. Over all power levels. Over all power levels Spurious<-36dBm, VRAMP =0.2V to 1.6V, RBW=3MHz Load impedance presented at RF OUT pad
0 Total Efficiency (PAE) Input Power for Max Output Folding Conversion Gain 45 +2 51 35 +4 -5 +6
dBm % % dBm dB
Output Noise Power Forward Isolation Second Harmonic Third Harmonic All other Non-Harmonic Spurious Cross Band Coupling 2F0 Input Impedance Input VSWR Output Load VSWR Output Load Ruggedness Output Load Impedance Note: VRAMP,MAX =3/8*VBATT +0.18<1.6V
-86
-84 -25 -5
dBm dBm dBm dBm dBm dBm
-30
-7 -36 -20
50 2.5:1 6:1 10:1 50
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Parameter
Power Control VRAMP, GSM850 GMSK Mode
Power Control "ON" Power Control "OFF" Power Control Range VRAMP Input Capacitance VRAMP Input Current Turn On/Off Time 0.2 33 15 10 4 1.6 0.25 V V dB pF A S Max POUT, Voltage supplied to the input Minimum POUT, Voltage supplied to the input. VRAMP =0.2V to 1.6V DC to 2MHz VRAMP =1.6V VRAMP =0V to 1.6V Temp=+25 C, VCC =3.5V, BandSelect=Low, VMODE =High, VRAMP =VRAMP,MAX, Freq=824MHz to 849MHz, 25% Duty Cycle, Pulse Width=1154s 824 +28.5 +26.5 Total Efficiency (PAE) Gain Gain Temperature Coefficient EVM RMS 28.0 25 30.0 28.5 -0.03 2.0 3.5 5.0 ACPR and Spectrum Mask -36 -60 -34 -56 -63 Output Noise Power Forward Isolation Second Harmonic Third Harmonic All other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Output Load Ruggedness Output Load Impedance 6:1 10:1 50 Load impedance presented at RF OUT pad 50 2.5:1 -85 -40 -84 -30 -7 -7 -36 31.5 +29.0 849 MHz dBm dBm % dB dB db/ % % dBc dBc dBc dBm dBm dBm dBm dBm Over all power levels Spurious<-36dBm, VRAMP =0.2V to 1.6V, RBW=3MHz Temp=-20C to +85C Temp=-20C to +85C, VCC =3.2V to 4.8V POUT <28.5dBm POUT <26.5dBm, VCC =3.2V to 4.8V, <2.5:1VSWR, All angles At 200kHz in 30kHz BW, POUT <28.5dBm At 400kHz in 30kHz BW, POUT <28.5dBm At 600kHz to 1800kHz in 30kHz BW, POUT <28.5dBm RBW=100kHz, 869MHz to 894MHz, POUT >+5dBm TX Enable=0V, VRAMP = 0.2V, PIN =+6dBm Over all power levels Over all power levels Temp=-20C to +85C, VCC =3.2V At POUT,MAX, VCC =3.5V
Min.
Specification Typ.
Max.
Unit
Condition
GSM US 850MHz Band 8PSK Mode
Operating Frequency Range Output Power to Meet EVM and ACPR Spectrum
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Parameter Min. Specification Typ. Max. Unit Condition
Temp=+25 C, VCC =3.5V, BandSelect=Low, VMODE =Low, VRAMP =VRAMP,MAX, PIN =+4dBm Freq=880MHz to 915MHz, 25% Duty Cycle, Pulse Width=1154s, TX EN=High 880 +34.5 +35.0 +32.5 0 Total Efficiency (PAE) Input Power for Max Output Folding Conversion Gain 45 +2 55 35 +4 +6 -5 915 MHz dBm dBm dBm % % dBm dB F0 =915MHz, other signal 895MHz at -40dBm, measured at 935MHz in 100kHz RBW (Max Power) RBW=100kHz, 925MHz to 935MHz, POUT >+5dBm RBW=100kHz, 935MHz to 960MHz, POUT >+5dBm TX_ENABLE=0V, VRAMP =0.2, PIN =+6dBm Over all power levels Over all power levels Measured at DCS/PCS port. Over all power levels. Over all power levels Spurious<-36dBm, VRAMP =0.2V to 1.6V, RBW=3MHz Load impedance presented at RF OUT pad Temp = 25C, VCC =3.5V, VRAMP =VRAMP,MAX Temp=+85oC, VBATT =3.0V, VRAMP =VRAMP,MAX VRAMP =0.2V At POUT,MAX, VCC =3.5V At POUT =31.5dBm
GSM US 900MHz Band
Operating Frequency Range Maximum Output Power
Output Noise Power
-82 -86
-80 -84 -25 -5 -7 -36 -20
dBm dBm dBm dBm dBm dBm dBm
Forward Isolation Second Harmonic Third Harmonic All other Non-Harmonic Spurious Cross Band Coupling 2F0 Input Impedance Input VSWR Output Load VSWR Output Load Ruggedness Output Load Impedance Note: VRAMP,MAX =3/8*VBATT +0.18<1.6V 6:1 10:1 50 50
2.5:1
Power Control VRAMP, GSM900 GMSK Mode
Power Control "ON" Power Control "OFF" Power Control Range VRAMP Input Capacitance VRAMP Input Current Turn On/Off Time 0.2 33 15 10 4 1.6 0.25 V V dB pF A S Max POUT, Voltage supplied to the input Minimum POUT, Voltage supplied to the input. VRAMP =0.2V to 1.6V DC to 2MHz VRAMP =1.6V VRAMP =0V to 1.6V
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Parameter
GSM 900MHz Band 8PSK Mode
Operating Frequency Range Output Power to Meet EVM and ACPR Spectrum Total Efficiency (PAE) Gain Gain Temperature Coefficient EVM RMS 28.0 880 +28.5 +26.5 25 29.5 28.0 -0.03 2.0 3.5 5.0 ACPR and Spectrum Mask -36 -60 -34 -56 -63 Output Noise Power Forward Isolation Second Harmonic Third Harmonic All other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Output Load Ruggedness Output Load Impedance 6:1 10:1 50 Load impedance presented at RF OUT pad 50 2.5:1 -85 -84 -25 -7 -7 -36 31.0 +29.0 915 MHz dBm dBm % dB dB db/ % % dBc dBc dBc dBm dBm dBm dBm dBm Over all power levels Spurious<-36dBm, VRAMP =0.2V to 1.6V, RBW=3MHz Temp=-20C to +85C Temp=-20C to +85C, VCC =3.2V to 4.8V POUT <28.5dBm POUT <26.5dBm, VCC =3.2V to 4.8V, <2.5:1VSWR, All angles At 200kHz in 30kHz BW, POUT <28.5dBm At 400kHz in 30kHz BW, POUT <28.5dBm At 600kHz to 1800kHz in 30kHz BW, POUT <28.5dBm RBW=100kHz, 935MHz to 960MHz, POUT >+5dBm TX Enable=0V, VRAMP = 0.2V, PIN =+6dBm Over all power levels Over all power levels Temp=-20C to +85C, VCC =3.2V At POUT,MAX, VCC =3.5V
Min.
Specification Typ.
Max.
Unit
Condition
Temp=+25 C, VCC =3.5V, BandSelect=Low, VMODE =High, VRAMP =VRAMP,MAX, PIN =+4dBm Freq=880MHz to 915MHz, 25% Duty Cycle, Pulse Width=1154s
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Parameter
Overall (DCS/PCS Mode) GMSK Mode
Operating Frequency Range Maximum Output Power 1710 +32 31.5 Total Efficiency (PAE) Recommended Input Power Range Folding Conversion Gain 43 +2 +33 32.5 30 49 45 +4 -5 +6 1910 MHz dBm dBm dBm % % dBm dB F0 =849MHz, other signal 829MHz at -40dBm, measured at 869MHz in 100kHz RBW (Max Power) F0 =1785, RBW=100kHz, 1805MHz to 1880MHz F0 =1910, RBW=100kHz, 1930MHz to 1990MHz TX Enable=0V, VRAMP =0.2, PIN =+6dBm Over all power levels Over all power levels Temp=+25 C, VCC =3.5V, VRAMP =1.6V, 1710MHz to 1785MHz 1850MHz to 1910MHz Temp=+85oC, VBATT =3.0V, VRAMP =VRAMP_MAX At POUT,MAX, VCC =3.5V, 1710MHz-1785MHz 1850MHz-1910MHz
Min.
Specification Typ.
Max.
Unit
Condition
Temp=+25 C, VCC =3.5V, PIN =+4dBm BandSelect=High, VRAMP =VRAMP,MAX, Freq=1710MHz to 1910MHz, 25% Duty Cycle, Pulse Width=1154s
Output Noise Power (DCS) Output Noise Power (PCS) Forward Isolation Second Harmonic Third Harmonic All other Non-Harmonic Spurious Cross Band Coupling 2F0 Input Impedance Input VSWR Output Load VSWR Output Load Ruggedness Output Load Impedance
-80 -80 -37
-77 -77 -30 -7 -7 -36
dBm dBm dBm dBm dBm dBm dBm
-60 50
-30 2.5:1
Over all power levels Spurious<-36dBm, VRAMP =0.2V to 1.6V RBW=3MHz Load impedance presented at the PCS/DCS RF OUT PIN
6:1 10:1 50
Power Control VRAMP, DCS/PCS GMSK
Power Control "ON" Power Control "OFF" Power Control Range VRAMP Input Capacitance VRAMP Input Current Turn On/Off TIme 0.2 33 15 10 4 1.6 0.25 V V dB pF A s Max. POUT, Voltage supplied to the input Min. POUT, Voltage supplied to the input VRAMP =0.2V to 1.6V DC to 2MHz VRAMP =1.6V VRAMP =0Vto1.6V
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RF3145
Parameter
1710MHz to 1785MHz 8PSK Mode
Operating Frequency Range Output Power to Meet EVM and ACPR Spectrum 1710 27.5 28.0 1785 MHz dBm Temp=25C, VCC =3.5V, Freq=1710MHz to 1785MHz, VRAMP =VRAMP,MAX Temp=-20C to +85C, VCC =3.2V At POUT,MAX VCC =3.5V Temp=-20C to +85C Temp=-20C to +85C, VCC =3.2V to 4.8V POUT <27.5dBm POUT <25.5dBm, VCC =3.2V to 4.8V, <2.5:1VSWR, All angles At 200kHz in 30kHz BW, POUT <27.5dBm At 400kHz in 30kHz BW, POUT <27.5dBm At 600kHz to 1800kHz in 30kHz BW, POUT <27.5dBm F0 =1785, RBW=100kHz, 1805MHz to 1880MHz TX Enable=0V, VRAMP =0.2, PIN =+6dBm Over all power levels Over all power levels
Min.
Specification Typ.
Max.
Unit
Condition
Temp=25C, VCC =3.5V, BandSelect=High, Freq=1710MHz to 1785MHz, PIN =+4dBm VRAMP =VRAMP,MAX, 25% Duty Cycle, Pulse Width=1154s
25.5 Total Efficiency (PAE) Gain Gain Temperature Coefficient EVM 32.5 25 36 34.5 -0.03 2.0 3.5 5.0 ACPR and Spectrum Mask -36 -58 -34 -56 -63 Output Noise Power (DCS) Forward Isolation Second Harmonic Third Harmonic All other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Output Load Ruggedness Output Load Impedance 6:1 10:1 50 50 2.5:1 -80 -77 -30 -7 -7 -36 37.5
dBm % dB dB db/ % % dBc dBc dBc dBm dBm dBm dBm dBm
Over all power levels Spurious<-36dBm, VRAMP =0.2V to 1.6V RBW=3MHz Load impedance presented at the DCS RF OUT PIN
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Parameter
1850MHz to 1910MHz 8PSK Mode
Operating Frequency Range Output Power to Meet EVM and ACPR Spectrum 1850 27.5 28.0 1910 MHz dBm Temp=25C, VCC =3.5V, Freq=1850MHz to 1910MHz, VRAMP =VRAMP,MAX Temp=-20C to +85C, VCC =3.2V At POUT,MAX VCC =3.5V Temp=-20C to +85C Temp=-20C to +85C, VCC =3.2V to 4.8V POUT <27.5dBm POUT <25.5dBm, VCC =3.2V to 4.8V, <2.5:1VSWR, All angles At 200kHz in 30kHz BW, POUT <27.5dBm At 400kHz in 30kHz BW, POUT <27.5dBm At 600kHz to 1800kHz in 30kHz BW, POUT <27.5dBm F0 =1910, RBW=100kHz, 1930MHz to 1990MHz TX Enable=0V, VRAMP =0.2, PIN =+6dBm Over all power levels Over all power levels
Min.
Specification Typ.
Max.
Unit
Condition
Temp=25C, VCC =3.5V, BandSelect=High, Freq=1850MHz to 1910MHz, VRAMP =VRAMP,MAX, 25% Duty Cycle, Pulse Width=1154s
25.5 Total Efficiency (PAE) Gain Gain Temperature Coefficient EVM 32.50 25 35.5 34.0 -0.03 2.0 3.5 5.0 ACPR and Spectrum Mask -36 -58 -34 -56 -63 Output Noise Power (PCS) Forward Isolation Second Harmonic Third Harmonic All other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Output Load Ruggedness Output Load Impedance 6:1 10:1 50 50 2.5:1 -80 -77 -30 -7 -7 -36 37.5
dBm % dB dB db/ % % dBc dBc dBc dBm dBm dBm dBm dBm
Over all power levels Spurious<-36dBm, VRAMP =0.2V to 1.6V RBW=3MHz Load impedance presented at the PCS RF OUT PIN Specifications Nominal operating limits, POUT <+33dBm 50% Duty Cycle, pulse width=2308s DC Current at POUT,MAX PIN <-30dBm, VRAMP =0V, Temp=-40C to +85C
Overall Power Supply
Power Supply Voltage 3.0 3.0 Power Supply Current 2.0 1 VMODE Voltage "Low" VMODE Voltage "High" 0.0 1.5 0.0 2.8 10 0.7 3.0 3.5 4.8 4.3 V V V A A V V
Note: VRAMP,MAX =3/8*VBATT +0.18<1.6V
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Pin 1 2 3 4 5 Function Description DCS/PCS IN RF input to the DCS/PCS band. This is a 50 input.
BAND SELECT
Allows external control to select the GSM or DCS/PCS band with a logic high or low. A logic low enables the GSM band whereas a logic high enables the DCS/PCS band. This signal enables the PA module for operation with a logic high. Once TX Enable is asserted the RF output level will increase to 0dBm. Power supply for the module. This should be connected to the battery. This signal selects 8PSK mode with a logic "high" (1.5V to 3.0V), and selects GMSK mode with a logic "low" (0V to 0.7V). When the VMODE switch is enabled "high", the gain in the GSM band is reduced by bypassing the first stage amplifier. When the VMODE is "low", all stages are active. Ramping signal from DAC. A simple RC filter may need to be connected between the DAC output and the VRAMP input depending on the baseband selected. The ramping profiles shown later in the data sheet are recommended profiles for meeting the GSM specification for burst timing and transient spectrum. RF input to the GSM band. This is a 50 input. Not connected. RF output for the GSM band. This is a 50 output. The output load line matching is contained internal to the package. Not connected. RF output for the DCS/PCS band. This is a 50 output. The output load line matching is contained internal to the package. Not connected.
Interface Schematic
TX ENABLE VBATT VMODE
6
VRAMP
7 8 9 10 11 12 Pkg Base
GSM IN NC GSM OUT NC DCS/PCS OUT NC GND
Rev A4 DS050919
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Package Drawing
1
1.70 1.45
10.000.10
0.4500.075 10.000.10 1.275
7.227 7.325 7.500 TYP 8.275 8.300 TYP 9.204 9.242 9.646
1
9.600 TYP 8.800 TYP 8.200 TYP 7.400 TYP 6.800 TYP 6.000 TYP 5.475 4.525 4.000 TYP 3.200 TYP 2.600 TYP 1.800 TYP 1.200 TYP 0.400 TYP 0.000 0.000 0.400 TYP 1.200 TYP 1.797 TYP 2.600 TYP 3.200 TYP 4.000 TYP 4.600 TYP 5.400 TYP 6.000 TYP 6.800 TYP 7.330 8.280 8.800 TYP 9.600 TYP
8.72 6.15 5 6 5.10 5.92 0 5 5.400 TYP 4.600 TYP 4.075 3.955 1.275
Pin Out
PIN #1 NC
DCS/PCS IN
DCS/PCS OUT
BAND SELECT
TX EN
VBATT
NC
10.0000
VMODE
VRAMP
GSM IN NC
GSM OUT
10.0000
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RF3145
Application Schematic
DCS/PCS IN BAND SELECT TX ENABLE VBATT VMODE VRAMP GSM IN 15 k** 50 strip 50 strip 12 1 2 3 4 5 6 7 8 9 50 strip 10 11 50 strip DCS/PCS OUT
GSM OUT
** Used to filter noise and spurious from base band.
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
P1 1 GND P2-1 CON1 DCS/PCS IN 50 strip 12 1 BAND SELECT TX ENABLE VBATT 3.3 F* 15 k** 50 strip 2 3 4 VMODE 5 6 7 8 9 50 strip *** 10 11 P2 1 VCC CON1
50 strip ***
DCS/PCS OUT
VRAMP GSM IN
GSM OUT
*Not required in most applications. ** Used to filter noise and spurious from baseband. *** 0.05 dB loss for GSM 0.15 dB loss for DCS
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Dual Mode Operation
MODE GSM EDGE
FIXED
Linear ramp from AGC Amplifier/Source (GSM Burst Ramp Signal)
RF INPUT
VRAMP
Ramp from 0.2V to 1.6V (GSM Burst Ramp Signal) FIXED
TX ENABLE
High (Normal) Low (Isolation) High (Normal) Low (Isolation)
VMODE
Low High
RF3145 Power Amplifier Simplified Block Diagram of a Single Band
TX ENABLE VRAMP VBATT
H(s)
RF IN
RF OUT
TX ENABLE AGC Amplifier
Power On Sequence
3.0 V to 4.8 V VBATT Power on Sequence: Apply VBATT Apply Band Select Apply RF drive Apply TX_Enable & VRAMP in unison The Power Down sequence is in reverse order to the Power On Sequence. VRAMP starts 1us after TX_Enable 0.15 V to 1.6 V VRAMP settles at 0.2 V 1us before TX_Enable goes low *NOTE: VBATT must be present before applying VREG to protect the ESD circuit from damage.
> 1.5 V
TX_ENABLE
VRAMP
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RF3145
Theory of Operation
Overview The RF3145 is a dual-mode, quad-band power amplifier module that is compatible with both GSM and EDGE applications. The device operates in a broad frequency range that includes the GSM850, GSM900, DCS1800, and PCS1900 frequency bands. Integrated band select, mode select, and power control features are also integrated to provide digital control of various features. Band select provides digital selection of the GSM850/900 or DCS1800/PCS1900 band. VMODE provides digital control of the gain in the GSM900 band. Due to gain expansion at input powers below the 1dB compression point, low gain mode is provided to maintain the noise power performance in EDGE applications. However, this feature is not required in the DCS1800/PCS1900 bands. Therefore, VMODE controls only the gain in the GSM850/900 band. (This feature is not provided in the DCS/PCS band.) The integrated power control feature employs an indirect closed loop method that uses collector control to regulate output power. Collector control design architecture has several advantages, including simplifying the phone design, as well as minimizing gain and linearity variation in EGDE applications. Integrated power control eliminates the need for a complicated control loop design. The indirect closed loop is fully self-contained and does not require loop optimization. It can be driven directly from the DAC output in the baseband circuit. The RF3145 mode of operation is a function of the input power level and the VMODE logic level. In GSM applications, the input power is held constant in the range of +2dBm to +5dBm, and the output power is controlled using the VRAMP input. The required input power for GSM/GPRS applications is typically 3dB to 4dB higher than the 1dB compression point. GSM/GPRS applications use GMSK modulation, which is constant envelope and is not sensitive to amplitude non-linearities. Therefore the power amplifier may be operated in deep class AB which offers high efficiency. However, in EDGE applications, the 3/8 rotated 8-PSK constellation shown in Figure 1 contains both phase and amplitude information.
Figure 1. EDGE 3Pi/8 Rotated 8-PSK Constellation Therefore, EDGE applications require a linear power amplifier to transfer EDGE modulation with minimal distortion. Changing VRAMP in linear applications will cause distortion to the EDGE modulated signal, and is not recommended. If the VRAMP signal is lowered in EDGE applications, the voltage on the collectors of the power amplifiers will also be lowered (lower than the 1dB compression point). In EDGE applications, the VRAMP input should be held constant at VRAMP(MAX), and the input power is ramped to meet the EDGE burst mask. Typical EDGE systems use a VGA to provide this RF ramp input to the power amplifier.
Theory of Operation
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The indirect closed loop is essentially a closed loop method of power control that is invisible to the user. Most power control systems in GSM sense either forward power or collector/drain current. The RF3145 does not use a power detector. A highspeed control loop is incorporated to regulate the collector voltages of the amplifier while the stages are held at a constant bias. The VRAMP signal is multiplied and the collector voltages are regulated to the multiplied VRAMP voltage. The basic circuit is shown in the following diagram.
VBATT TX ENABLE VRAMP
H(s)
RF IN TX ENABLE
RF OUT
By regulating the power, the stages are held in saturation across all power levels. As the required output power is decreased from full power down to 0dBm, the collector voltage is also decreased. This regulation of output power is demonstrated in Equation 1 where the relationship between collector voltage and output power is shown. Although load impedance affects output power, supply fluctuations are the dominate mode of power variations. With the RF3145 regulating collector voltage, the dominant mode of power fluctuations is eliminated.
P dBm
( 2 V CC - V SAT ) = 10 log -------------------------------------------3 8 R LOAD 10
2
(Eq. 1)
There are several key factors to consider in the implementation of a transmitter solution for a mobile phone. Some of them are: * Effective efficiency (EFF) * Current draw and system efficiency * Power variation due to Supply Voltage * Power variation due to frequency * Power variation due to temperature * Input impedance variation * Noise power * Loop stability * Loop bandwidth variations across power levels * Burst timing and transient spectrum trade-offs * Harmonics Talk time and power management are key concerns in transmitter design since the power amplifier has the highest current draw in a mobile terminal. Considering only the power amplifier's efficiency does not provide a true picture for the total system efficiency. It is important to consider effective efficiency which is represented by EFF.. (EFF considers the loss between the PA and antenna and is a more accurate measurement to determine how much current will be drawn in the application). EFF is defined by the following relationship (Equation 2):
m
PN - PIN
-------------------------------- 100 EFF = n = 1 P DC
(Eq. 2) Where PN is the sum of all positive and negative RF power, PIN the input power and PDC is the delivered DC power. In dB the formula becomes (Equation 3):
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Rev A4 DS050919
RF3145
10 - 10 EFF = -----------------------------------------------V BAT I BAT 10
P PA + P LOSS ----------------------------10 P IN ------10
(Eq. 3)
Where PPA is the output power from the PA, PLOSS the insertion loss, PIN the input power to the PA, and PDC the delivered DC power. The RF3145 improves the effective efficiency by minimizing the PLOSS term in the equation. A directional coupler may introduce 0.4dB to 0.5dB loss to the transit path. To demonstrate the improvement in effective efficiency consider the following example: Conventional PA Solution:
PPA = +33.5 dBm PIN = +3 dBm PLOSS = -0.4 dB VBAT = 3.5 V IBAT = 1.16 A
RF3145 Solution:
EFF = 50.3%
PPA = +33.5 dBm PIN = +3 dBm PLOSS = 0 dB VBAT = 3.5 V IBAT = 1.16 A
The RF3145 solution improves effective efficiency 5percent.
hEFF = 55.16%
Output power does not vary due to supply voltage under normal operating conditions if VRAMP is sufficiently lower than VBATT. By regulating the collector voltage to the PA, the voltage sensitivity is essentially eliminated. This covers most cases where the PA will be operated. However, as the battery discharges and approaches its lower power range, the maximum output power from the PA will also drop slightly. In this case it is important to also decrease VRAMP to prevent the power control from inducing switching transients. These transients occur as a result of the control loop slowing down and not regulating power in accordance with VRAMP. The switching transients due to low battery conditions are regulated by incorporating the following relationship limiting the maximum VRAMP voltage (Equation 4). Although no compensation is required for typical battery conditions, the battery compensation required for extreme conditions is covered by the relationship in Equation 4. This should be added to the terminal software.
3 V RAMP -- V BATT + 0.18 8
(Eq. 4)
NOTE: Output power is limited by battery voltage. The relationship in Equation 4 does not limit output power. Equation 4 limits the VRAMP voltage to correspond with the battery voltage. Due to reactive output matches, there are output power variations across frequency. There are a number of components that can make the effects greater or less.
Rev A4 DS050919
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RF3145
The components following the power amplifier often have insertion loss variation with respect to frequency. Usually, there is some length of microstrip following the power amplifier. There is also a frequency response found in directional couplers due to variation in the coupling factor over frequency, as well as the sensitivity of the detector diode. Since the RF3145 does not use a directional coupler with a diode detector, these variations do not occur. Input impedance variation is found in most GSM power amplifiers. This is due to a device phenomena where CBE and CCB (CGS and CSG for a FET) vary over the bias voltage. The same principle used to make varactors is present in the power amplifiers. The junction capacitance is a function of the bias across the junction. This produces input impedance variations as the VAPC voltage is swept. Although this could present a problem with frequency pulling the transmit VCO off frequency, most synthesizer designers use very wide loop bandwidths to quickly compensate for frequency variations due to the load variations presented to the VCO. The RF3145 presents a very constant load to the VCO. This is because all stages of the RF3145 are run at constant bias. As a result, there is constant reactance at the base emitter and base collector junction of the input stage to the power amplifier. Noise power in PA's where output power is controlled by changing the bias voltage is often a problem when backing off of output power. The reason is that the gain is changed in all stages and according to the noise formula (Equation 5),
F TOT = F1 + F2 - 1 + --------------------------------- F3 - 1 G1 G1 G2
(Eq. 5)
the noise figure depends on noise factor and gain in all stages. Because the bias point of the RF3145 is kept constant, the gain in the first stage is always high and the overall noise power is not increased when decreasing output power. Power control loop stability often presents many challenges to transmitter design. Designing a proper power control loop involves trade-offs affecting stability, transient spectrum and burst timing. In conventional architectures, the PA gain (dB/V) varies across different power levels, and as a result the loop bandwidth also varies. With some power amplifiers it is possible for the PA gain (control slope) to change from 100dB/V to as high as 1000dB/V. The challenge in this scenario is keeping the loop bandwidth wide enough to meet the burst mask at low slope regions which often causes instability at high slope regions. The RF3145 loop bandwidth is determined by internal bandwidth, and the RF output load and does not change with respect to power levels. This makes it easier to maintain loop stability with a high bandwidth loop since the bias voltage and collector voltage do not vary. An often overlooked problem in PA control loops is that a delay not only decreases loop stability, it also affects the burst timing (for instance, when the input power from the VCO decreases (or increases) with respect to temperature or supply voltage). The burst timing then appears to shift to the right, especially at low power levels. The RF3145 is insensitive to a change in input power and the burst timing is constant and requires no software compensation. Switching transients occur when the up and down ramp of the burst is not smooth enough, or suddenly changes shape. If the control slope of a PA has an inflection point within the output power range, or if the slope is simply to steep, it is difficult to prevent switching transients. Controlling the output power by changing the collector voltage is (as described earlier) based on the physical relationship between voltage swing and output power. Furthermore all stages are kept constantly biased so inflection points are nonexistent.
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Rev A4 DS050919
RF3145
Harmonics are natural products of high efficiency power amplifier design. An ideal class "E" saturated power amplifier will produce a perfect square wave. Looking at the Fourier transform of a square wave reveals high harmonic content. Although this is common to all power amplifiers, there are other factors that contribute to conducted harmonic content as well. With most power control methods, a peak power diode detector is used to rectify and sense forward power. Through the rectification process, there is additional squaring of the waveform resulting in higher harmonics. The RF3145 addresses this by eliminating the need for the detector diode. Therefore, the harmonics coming out of the PA should represent the maximum power of the harmonics throughout the transmit chain. This is based on proper harmonic termination of the transmit port. The receive port termination on the T/R switch, as well as the harmonic impedance from the switch itself, will have an impact on harmonics. Should a problem arise, these terminations should be explored. NOTE: Output power is limited by battery voltage. The relationship in Equation 4 does not limit output power. Equation 4 limits VRAMP to correspond with the battery voltage.
1 2 3 4 5 6 7 14 13 12 11 10 9 8
From DAC
*Shaded area eliminated with Indirect Closed Loop using RF3145
Rev A4 DS050919
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RF3145
PCB Design Requirements
PCB Surface Finish The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3inch to 8inch gold over 180inch nickel. PCB Land Pattern Recommendation PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. PCB Metal Land and Solder Mask Pattern
A = 0.80 Sq. Typ. B = 0.95 x 0.87 Typ. C = 0.87 x 0.95
Dimensions in mm.
1.39 Typ.
2.07 2.40
4.60
A = 0.80 (mm) Sq. Typ. 8.40 Typ. 7.00 5.60 4.20 2.80 1.40 0.00
Pin 1
A A A A A A A
A
7.60
8.36 7.40 5.35 3.15 1.00
Pin 1
8.36
A A A A A A A
B A A A A A B
A
A
A A A A A A
A A A A A A A
A A A C A A A
8.40 Typ. 7.00 Typ. 5.60 Typ. 4.20 Typ. 2.80 Typ. 1.40 Typ.
A
0.80
0.04 0.00
A
A
A
7.60 8.40 Typ. 8.80 Typ.
0.00 0.80
0.00
1.40 Typ.
2.80 Typ.
4.20 Typ.
5.60 Typ.
7.00 Typ.
Metal Land Pattern
Solder Mask Pattern
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8.40 Typ.
Rev A4 DS050919

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